The present invention relates to a memory apparatus, which uses a volatile memory and a nonvolatile memory, and to a construction of a high-speed and inexpensive memory system.
In a memory system using a volatile memory and a nonvolatile memory, as described in JP-A-2001-5723, a method is available, in which a content of the nonvolatile memory is copied in the volatile memory when power is turned ON, and the volatile memory is accessed from a host and used. In this case, when power is turned OFF, a content of the volatile memory is copied in the nonvolatile memory, and a result of its processing is notified through an exclusive line to the host. Accordingly, power is safely turned OFF, and data is held even after the power is OFF.
In the above-described conventional art, data transfer between the volatile memory (DRAM) and the nonvolatile memory (flash memory) is carried out only when the power is turned ON or OFF. Thus, no consideration has been given to execution of the data transfer during use of the memory system after the power is ON. As the data transfer targets all the nonvolatile memories, transfer to a large-capacity memory takes time, and preparation until the memory system is ready to be used takes long. In the power-OFF state, since the exclusive line is used to notify the end of copying processing to the host, control is impossible by using only an existing nonvolatile memory interface. In addition, no consideration has been given to accessing of the nonvolatile memory from the host. Furthermore, no consideration has been given to a difference between a data transfer speed of the volatile memory and a data transfer speed of the nonvolatile memory.